1. Introduction
2. Testing sequence
2.1 Component tests
2.1.1 Introduction
2.1.2 Reception of parts
2.1.3 Bare Hybrid tests
2.1.4 Stuffed hybrid tests
2.1.5 Asic mounted hybrid tests
2.1.6 Detector tests
2.1.7 Fan in tests
2.2 Sub assembly tests
2.3 Module tests
2.4 Tests after shipping
3. Batch tests
3.1 Hybrids
3.2 Detectors
3.3 Detector test structures
4. Standard testing conditions
4.1 Chip tests
4.1.1 Check of hybrid supply currents
4.1.2 Hybrid temperature cycling
4.1.3 Burn in
4.1.4 Test vectors: Simple
4.1.5 Test vectors: Full
4.1.6 Test vectors: Data run
4.2 Detector tests
4.4 Fan-in tests
5. Database entries and criteria
see (WWW edition, Uni.Geneva): http://polux0.unige.ch/sctprd/doc/userguide/welcome.html
and (PC/Mac version, Uni Manchester): http://hepwww.ph.man.ac.uk/groups/atlas/SCTdatabase/Database.html
6. Infrastructure requirements
This document is a 'living document', liable to be updated at any time. It has grown initially from a series of presentations and discussions in the CERN GENEVA cluster which were then presented in the June 98 SCT week. Following the suggestions then given, each cluster rep. nominated a testing representative. In its present form it owes more to the efforts of the people who prepared QA documents in the UK and the many suggestions from testing representatives in each cluster. These people are consulted before each release of the document, and continue to contribute to the detailed procedures described here.
Suggestions should be sent to me, shaun.roe@cern.ch
After each preliminary circulation of the document to these people (and absorbing their comments), it is posted here for wider comment by the sct community.
The document is divided into six parts:
1) An introduction
2) A section giving overall testing procedure seen as a sequence, with cursory explanations of the tests and their aims. Web links to detailed explanations of section 3.
3) Batch tests, to be performed on a subset associated with production
4) Detailed specifications of the tests, with reference to other documents where appropriate, and a description of the likely equipment and manpower needed.
5) A list of variables extracted from the tests, with pass/fail criteria where appropriate.
6) Infrastructure requirements
I should like this document, initially, to be as complete as possible in terms of the possible tests to be performed. In actual production, and with experience, it will become clear which of the tests are actually necessary in terms of verifying the final production quality.
Despite the categorical tone, nothing is set in stone, everything is up for discussion.
I divide the testing into component(essentially hybrids and detectors), sub-assembly (check on metrology), and module (final tests). In addition to this sequence there is a section defining tests to be performed after each transport of the module or hybrid, to ensure that no damage has occurred in transit.
I define and use the following terms:
Bare hybrid: hybrid with no components or connectors
Stuffed hybrid: hybrid with passive components and connectors
ASIC mounted hybrid: stuffed hybrid with ASICs mounted
Module: Finished product, fully mounted with detectors.
I have tried to define as full a set of tests as may be initially necessary; these tests may be reassessed after a preproduction run and may be omitted or only performed on a sample of components.
I treat the hybrid and detectors separately and assume that the finished pieces at the end of this stage are : Electrically tested hybrids with chips on;Tested detectors ;Inspected (tested?) additional mounting pieces, including baseboard.
All parts are received and checked against
an inventory; where appropriate, manufacturers information is
entered in the database.
The pieces are visually inspected for obvious defects.
Some parts (which ones?) may be mechanically measured on a batch
basis to ensure they are within tolerance.
1. The manufacturer shall manufacture the hybrids adhering to standard IPC-6013 'Qualification and Performance specification for flexible printed boards'. For this purpose, the hybrids are to be regarded as 'class 3' circuitry.
2. The isolation of the HV line shall be tested up to 600V
1. The stuffed hybrid shall undergo thermal cycling ten times from -20°C to 20°C and then retested for continuity.
All temperatures are referred to the hybrid temperature sensor.
1. The hybrid is subject to a 'characterisation
test' at the operating temperature.
2. The hybrids are cycled ten times from -20°C to 20°C
while maintaining a constant check on the currents (this may be
redundant)
3. The first batch of hybrids are subjected to a 100 hour burn-in
at 20°C while checking the currents; subsequent batches may
be subjected to shorter burn-in.
4. Full test vectors checking each chip are sent, and the reply
read back and checked for conformity
5. A data run (detail http://sroe.home.cern.ch/sroe/Electric.pdf) is performed on each hybrid at the end of the
burn-in to ascertain the overall dynamic functionality and individual
channel characteristics (gain, pedestal, noise) at the operating
temperature.
1. IV characteristic up to 300 V
1. The fanins will be inspected optically for shorts
2. The fanins will be tested electrically
1. Reception tests, as defined in 2.4
2. Leakage current of the glued detector assembly
3. Intermediate metrology, 113 points per module, follow:
http://hepwww.ph.man.ac.uk/groups/atlas/module/su2.ps
1. Reception tests, as defined in section
2.4.
2. Detector IV
3. Detector I-time stability (in parallel with 6)
4. Cycle from +20 to -20 ten times, checking currents
5. Check metrology and dynamic deformation
6. Thermal image of an operating module
at 20 degrees, measured on the hybrid.
7. 100 hour burn in at the operating temperature, checking currents
8. Data run at the operating temperature
9. Source or laser data run at operating temperature.
1. Visual inspection
2. Check supply currents
3. Supply clock, read back clock divide by two.
Initially 10%, reducing to 5% during production
1. Detector depletion voltage
2. Strip integrity
3. Leakage current stability
4. Irradiation testing
Only on batches showing problems
1. Interstrip capacitance
2. Polysilicon bias resistance and interstrip resistance
3. Full strip test
4. Metal series resistance
5. Coupling capacitance
6. Implant sheet resistance
7. Flatband voltage
Gross check of chip and hybrid functionality
The currents should be checked, unless
specified, at room temperature with a current limited supply.
DACs should be at their nominal values. This requires the hybrid
to be clocked, reset, then configuration and DAC commands to be
sent.
The values are to be read 5 minutes after configuration to allow
the chips to warm up.
For the ABCD:
| Voltage [V] | Nominal current | Acceptable range | Supply limit | |
| Vdd | 4.0±0.1 |
40 mA per slave 50mA per master |
±20% | 600 mA |
| Vcc | 3.5±0.1 | 44 mA per chip | ±20% | 700 mA |
This test is intended to catch bad surface mount soldering and microcracks.
The hybrids are cycled from -20°C to 20°C ten times while connected to their supply, temperature measured on the hybrid
A thermal image should be taken to demonstrate that each chip is well coupled to the hybrid.
Acceptable current behaviour over
this range is yet to be ascertained.
Accelerated aging of the chips to catch infant mortality
The hybrids are mounted into a test bench.
The chips are initialised and then clocked (40MHz) and triggered
at 100kHz for the duration of the test. The temperature on the
hybrid is monitored, as are the currents. The hybrids are maintained
at 20°C for 100 hours. Alarm conditions should be set on the
temperature and currents, so that the power is cut if necessary.
Data may be read during the burn-in.
Gross check that each chip responds to a simple command
see: http://sroe.home.cern.ch/sroe/Electric.pdf
Every chip responds as predicted
Check that the chip responds to the full range of commands
see:http://sroe.home.cern.ch/sroe/Electric.pdf
Every chip responds as predicted
Optimisation of chip parameters on a chip by chip basis (e.g. strobe delay, bias and shaper currents), measurement of the chip characteristics: gain, pedestal, noise
see:http://sroe.home.cern.ch/sroe/Electric.pdf
Gains, pedestals and noise within acceptance
criteria (being defined); total number of bad channels within
acceptance.
Link for detector specification document (Maintained by Phil Allport)
Detailed testing procedures for all detectors, batch testing and irradiation testing are to be found in the QA documents maintained by Dave Robinson:
'ATLAS SCT Detector QA procedures'
'ATLAS SCT Detector Irradiation QA procedures'
'ATLAS Detector Qualification Tests'
Follow database links on title page.
It is assumed that the tests are carried out in a lab with access to standard electronics test equipment (oscilloscopes, multimeters etc.) In addition, a microscope with up to x80 magnification is assumed to be available for various visual inspections.
Tests described in 2.1.3, and section 4.1.
Environment chamber or test box, enabling temperature cycling from -20 to +50 deg C with humidity control (or nitrogen flushing) to prevent condensation.
Burn in and other tests are to be performed in parallel, so (at least!)two sets of the following are required:
Described in section 4.2; refer to linked documents for an exhaustive list.
Described in section 2.3
Metrology....?