This compilation of data is done by Y. Unno, independent of the company, for our convenience purpose only.
ATLAS FPC1.0 and several SVX-II Kapton hybrids are fabricated in the Mektec Corporation. Major differences in these hybrids from the design guidelines compiled below are the copper thickness and the diameters of the through-holes and their lands. The company recommends to have discussion in advance on the specifications outside the guidelines.
The Mektec design rule (in the leaflet which is reproduced in the following links) is for the guaranteed production. We have done 8 micron Cu for the (pre-) proto ATLAS FPC1.0 Kapton and SVX-II Kapton hybrids. The diameter of the through-hole and the land in the leaflet is much bigger than what they can do:
In the process of plating the wall of through-holes, top and the bottom surfaces are also plated. The thickness of plated Cu is 15 micron.
Since this thickness is to be added on the initial 8 micon layers, the top and the bottom metal layers become as thick as 23 microns. There is a process to mask other areas than the through-hole in the plating ("Mask through-hole plating"). This is possible for plain layers such as power or ground. This is not recommended for the trace layer, since the different copper thickness in the (through-hole) land and the line makes the etching of the pattern difficult.
In the next Kapton hybrids, we plan to do "mask process" for the bottom layer (Chip power layer in the ABCD), but not for the top layer (anyway, very small traces).
We also plan to "hatch" the power and the ground planes, e.g., 50%. This also helps to increase the impedance of the clock/signal lines.
In order to have a better heat conduction from the chip to the bridge, we will make a matrix of (heat conduction) through-holes under the chips.
In the Kapton design, because of its flexibility which is the advantage of the construction, there are several recommendations in the design in detail which are different from the designs in PC boards.
