From: KEKUX::"pier@nucleus.ps.uci.edu" "Steve Pier" 31-JAN-1996 09:09:53.21 To: unno@kekvax.kek.jp CC: pier@orion.oac.uci.edu Subj: Trigger Conditioning Board guide When I say 'DAQ' below, I just mean the logic that generates clocks, triggers, SOB, EOB, etc. **** You must remove the 100325 chip before applying a test signal to the **** **** LEMO connector. **** **** You must reset the TCB (by pressing the pushbutton or **** **** cycling the power) after changing the delay DIP switch. **** What the TCB is for: 1. Buffering the system clock and sending a TTL version of it to the ATC connector on the LL cards. 2. Synchronizing the trigger to the system clock. 3. Delaying the trigger an integral number of clock cycles via a pipeline. 4. Shaping the trigger pulse so that it is recognized as such by the module. 5. Generating a holdoff signal that tells the DAQ to disable triggers. This feature is useful for patching a HAC bug that causes data to be spewed endlessly if more than nine readouts are pending. Connections to the DAQ (differential ECL): connector: ECL I/O Connector (JP2) schematic: 'Input Conditioning and Holdoff' note: Unconnected ECL pairs are OK -- the result is a logic low. from the DAQ: EXT_CLK -- the system clock (e.g., 40 MHz) TRIGGER -- raw, unsynchronized trigger (active high) to the DAQ: TRIG -- the synchronized version of TRIGGER HOLDOFF -- tells the DAQ to stop sending triggers (when high) available, but probably not used: CLK -- a copy of the system clock IMPULSE -- like TRIG, but only high for one clock cycle per trigger OUT\ -- identical to T_ACCEPT\, but differential ECL Connections to the LL cards (TTL): connector: ATC (Auxiliary Trigger Control) Connector (JP1) schematic: 'Delay and Output Conditioning' note: Remove all RP5's on the SLL's except the last one; you may leave the RP4's installed. O_CLK -- a copy of the system clock T_ACCEPT\ -- the trigger signal to be sent to the modules (active low) LEMO Connector (J1): This connector is a convenient way to input TTL triggers for test purposes, but: **** You must remove the 100325 chip before applying a test signal to the **** LEMO connector And you must use the on-board oscillator as the clock source (see JP4 note below). Power Connector (H1): VCC == +5V VEE == -5V (~200 mA required) DIP switches: The DIP switches are intuitively encoded: up == 1, down == 0. The LSB is the rightmost switch. The impulse response looks like a graph of the inverse of the resulting signal on T_ACCEPT\, i.e., it looks like T_ACCEPT. Delay -- the number of clocks to delay T_ACCEPT\ Impulse Response -- a graph of the result of one input trigger. E.g., if this DIP switch is set to 1100011100, then: TRIG 00000000000111000000000000000000000000000000000000000000000 IMPULSE 00000000000010000000000000000000000000000000000000000000000 T_ACCEPT 00000000000000000000000000000000000000000000000001100011100 |-- determined by Delay DIP switch --| This assumes the TCB is jumpered for EDGE mode (in which the rising edge of TRIG causes a single impulse). Readout Time -- the maximum number of clocks a module requires to to read out one data set. This value is used by a digital one-shot to simulate module readout. Max Trigs (MT, SW5) -- the number of triggers (that have not been read out) above which the HOLDOFF signal becomes active. If this DIP switch is set to its maximum (15), then HOLDOFF never goes active. Jumpers: JP4 -- selects either the external clock (EXT_CLK) or the on-board crystal oscillator (INT_CLK) as the source of the TCB's CLK signal. I shipped the board with the jumper set for INT_CLK, so you don't need to supply an external clock for initial tests. JP3 -- selects two options, EDGE and LOC_HOLD If the EDGE jumper is not installed, then EDGE == 1, and a rising edge on TRIGGER causes IMPULSE to be active for a single clock cycle. If the jumper is not installed, then EDGE == 0, and IMPULSE will be high for as many clock cycles as TRIGGER is high (level-triggered). For the Aug/Sep test I suggest that the jumper should not be installed. If the LOC_HOLD jumper is not installed, then LOC_HOLD == 1, and the TCB gates triggers with HOLDOFF so that no triggers are sent to the modules when HOLDOFF is active. If the jumper is installed, then LOC_HOLD == 0, and the TCB does not locally gate triggers with HOLDOFF-- it is expected that some external circuit stops sending triggers when HOLDOFF is active. For initial convenience (to keep the HAC's from spewing endlessly), remove the jumper. At the Aug/Sep tests, the jumper should be installed to insure that the modules receive all the triggers that are issued (i.e., the DAQ will be responsible for not sending triggers when it sees HOLDOFF high). TRIG note: TRIG is solely dependent on TRIGGER and CLK--it is not affected by DIP switches or jumpers (except the internal/external CLK select jumper). It can be input to a TDC, along with TRIGGER, to measure how close the trigger was to the system clock. TRIGGER is synchronized **twice** to form TRIG. HOLDOFF notes: An up/down counter in the Input/Holdoff GAL increments once for each IMPULSE (i.e., once per trigger) and decrements each time a readout completes. The TCB does not really know when a readout completes--it just simulates readout locally by firing a digital one shot (whose output is the signal READ). This oneshot is fired (if it is not already firing) if the up/down counter is not zero. The up/down counter is sticky: it will not count up beyond 15 and it will not count down below 0. In summary: count up if IMPULSE is active count down if READ goes from active to inactive FIRE oneshot if (READ is inactive) AND (the up/down counter != 0) do not count above 15 or below 0 This entire process happens before the trigger pipeline delay (set on the Delay DIP switch). So, for example, if Max Trigs is set to 7, and eight triggers arrive within 30 clock cycles of each other, it is possible that HOLDOFF will go active before any of the triggers have even made it out of the delay pipeline. Convolution notes: The Convolution GAL convolves the IMPULSE signal with the setting of the Impulse Response DIP switch. So if the module requires T_ACCEPT\ to be active for a single clock cycle, just turn on one of the Impulse Response switches. If a module recognizes a 101 as a trigger, then just set the DIP switch to 1010000000. The impulse response can also be used to create closely-spaced triggers, e.g., for two triggers five clock cycles apart, set the DIP switch to 1000010000. This will cause two triggers to be sent to the module for every one trigger from the DAQ. Also, the Impulse Response DIP switch might be more convenient for fine-tuning the trigger delay than using the Delay DIP switch (which uses binary and requires a reset to take effect)-- e.g., 0010000000 is 1000000000 delayed by two clocks.