From pier@positron.ps.uci.edu Fri Aug 28 11:53:58 1998
Date: Thu, 27 Aug 1998 10:55:17 -0700
From: Steve Pier 
To: UNNO Yoshinobu 
Cc: Tom Fahland ,
    Steve_Pier ,
    Gareth_Moorhead ,
    Peter_PHILLIPS 
Subject: Re: TCC connection

TCC users:

I. Clock Jitter
---------------
The TCC's on-board oscillator chip (TCC X1) may cause significant clock jitter
if an external clock source is used with the TCC.  The source of the problem
seems to be the clock multiplexer (TCC U18), which has both on-board and
external clock sources as inputs.

Avoid this problem with some combination of:

  not using an external clock source
  bypassing the mux by setting the JP2 jumper to 'EXT' instead of 'MUX'
  removing the oscillator chip (TCC X1)
    

If the oscillator chip is removed, an extra precaution is to install a wire
between pins 4 and 5 of the oscillator socket.  This will ground the mux input
that was formerly driven by the oscillator.


II. Driving multiple SLL's with a single TCC
--------------------------------------------

A single TCC may be used to drive multiple SLL's.


1. For the DSP carrying the TCC, install jumpers at SLL JP10.  These jumpers
connect signals from the TCC to the Auxiliary Trigger Control (ATC) connector
(SLL JP11).

2. For all other DSP's, remove any jumpers at SLL JP10.  This will disconnect
the stubs that are routed to the TCC sockets on the DSP.

3. For the DSP most distant from the DSP carrying the TTC, install the
terminator packs at SLL RP4 and RP5.  These terminator packs are 120 ohms with
pin 1 common, suitable for terminating ribbon cables.

4. For all other DSP's, remove the terminators at RP4 and RP5.

5. Install a ribbon cable to connect the ATC connectors (SLL JP11) of all DSP's.


For more on connector pinouts related to the TCC, see:

I don't know why this html file displays improperly in Netscape Navigator.  It
displays ok in Explorer.

Note:  logic signals on the DSP's JP1 are differential ECL!

Note:  for proper line termination, a ribbon cable should be used to connect
signals to the DSP's JP1.


You need to input your trigger at EXT_TRIG (== DI_8) on the DSP's JP1, pins 9
(true) and 10 (inverted).

I do not know if ABCD works well with the TCC's on-board clock.  If not, supply
an external clock at EXT_CLK (== DI_10) on the DSP's JP1, pins 5 (true) and 6
(inverted).  See the related note below.


The trigger pulse should be >> 25 ns wide.  Use 100 ns just to be safe.

A terminator is required at DSP's RT2 (seven separate 110 ohm resistors).

Jumpers are required on the SLL at JP10.  These jumpers connect the TCC signals
to the SLL and to the ATC connector on the SLL (JP11).  JP10 and JP11 are shown
on the 'DSP Interface' page of the SLL schematic.


*** Important ***  see the notes below.

For debugging, you can see TCC output at the SLL's JP11 or JP10.  See the 'DSP
Interface' SLL schematic.
L_12 is the clock.  L_8 is T_MARK\; it should pulse low for 25 ns per input
trigger.  L_9 is T_ACCEPT\; for each trigger, it should output the programmed
impulse response pattern (i.e., the Level 1 trigger fast command, 110), but
inverted.


Steve

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