From pier@positron.ps.uci.edu Tue Sep  1 10:55:55 1998
Date: Mon, 31 Aug 1998 10:14:54 -0700
From: Steve Pier <pier@positron.ps.uci.edu>
To: UNNO Yoshinobu <unno@post.kek.jp>
Cc: Steve_Pier <Pier@nucleus.ps.uci.edu>,
    Peter_PHILLIPS <P.W.Phillips@rl.ac.uk>,
    Gareth_Moorhead <moorhead@liszt.ph.unimelb.EDU.AU>,
    Tom Fahland <fahland@positron.ps.uci.edu>
Subject: Re: TCC

Nobu:

> 4) Jumpers on JP10 of SLL (to look the clock on the 15th pair of JP11 of
>    SLL)

Ok. But these jumpers are required for more than just looking at the clock. 
They also connect the clock to the SLL.


> 3) Clock selection, JP2 of TCC, to EXT

Look for a TTL clock at this jumper.

If no clock, then check that your dif ECL input to DSP JP1 is valid ECL levels: 
approx -1/-2 V.

The translation from ECL to TTL is performed on the DSP, U2.  The ECL translator
uses -5V, derived from VME's -12V.  You can check -5V on the SLL, either at H1
or JP13.  Both are labelled on the silkscreen.  If no -5V, then check that a
jumper is installed on the VME board at JP6.  The jumper should be in the '7905'
position.

>   There is JP1 pins on the TCC.  No jumper is set.  Is this correct?

Yes.

> The oscillator has 4 leads.  Which is the pins 4 and 5?  (Where is 5?)


The oscillator pins are numbered as though the oscillator were an 8-pin chip. 
Pin 1 is the square pin.  Ignore the '1' on the silkscreen--that is for the
XILINX chip.

     X1
   1    8
  (2)  (7)
  (3)  (6)
   4    5

Steve